The move to nanosheet transistors is a boon for SRAM
Last week at the IEEE International Solid State Circuits Conference (ISSCC), two of the biggest rivals in advanced chipmaking, Intel and TSMC, detailed the capabilities of the key memory circuits, SRAM, built using their newest technologies, Intel 18a and TSMC N2. Chipmakers' ability to keep scaling down circuits has slowed over the years—but it's been particularly difficult to shrink SRAM, which is made up of large arrays of memory cells and supporting circuits. The two companies' most densely packed SRAM block provides 38.1 megabits per square millimeter, using a memory cell that's 0.021 square micrometers. That density amounts to as much as a 23 percent boost for Intel and a 12 percent improvement for TSMC. Somewhat surprisingly, that same morning Synopsys unveiled an SRAM design that achieved the same density using the previous generation of transistors, but it operated at less than half the speed. The Intel and TSMC technologies are the two companies' first use of a new transistor architecture, called nanosheets. (Samsung transitioned to nanosheets a generation earlier.) In previous generations, current flows through the transistor via a fin-shaped channel region. The design means that increasing the current a transistor can drive—so that circuits can operate faster or involve longer interconnects—requires adding more fins to the device. Nanosheet devices do away with the fins, exchanging them for a stack of silicon ribbons. Importantly, the width of those nanosheets is adjustable from device to device, so current can be increased in a more flexible fashion. "Nanosheets seem to allow SRAM to scale better than in other generations," says Jim Handy, chief analyst at memory consulting firm Objective Analysis. Flexible Transistors Make Smaller, Better SRAM An SRAM cell stores a bit in a six-transistor circuit. But the transistors are not identical, because they have different demands on them. In a FinFET-based cell, this can mean building two pairs of the…