RISC-V Bytes: Introduction to Instruction Formats

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RISC-V Bytes: Introduction to Instruction Formats

This is part of a series on the blog where we explore RISC-V by breaking down real programs and explaining how they work. You can view all posts in this series on the RISC-V Bytes page.

So far in this series, we have been looking at the assembly generated when compiling relatively simple programs. At this point, we have seen instructions that perform a wide variety of operations. Let's take another look at our minimal example from the Passing on the Stack post:

minimal.c

#include int sum( int one, int two) { return one + two; } int main() { printf( "The sum is: %d

" , sum( 1 , 2 )); return 0 ; }

riscv64-unknown-elf-gcc -O3 -fno-inline -march=rv64g minimal.c

Hold up a minute, what is that -march=rv64g doing in there? We didn't compile with that flag in the last post, but we are providing it here to disable instruction compression. The default march for our toolchain is rv64gc (or more specifically rv64imafdc ), but we are removing the C extension, which indicates that a machine supports instruction compression. In a future post we will explore how compression improves code size and why it makes our generated assembly look different. You may already notice some changes in the output below!

(gdb) disass main Dump of assembler code for function main: 0x00000000000100b0 : addi sp,sp,-16 0x00000000000100b4 : li a1,2 0x00000000000100b8 : li a0,1 0x00000000000100bc : sd ra,8(sp) 0x00000000000100c0 : jal ra,0x101b8 0x00000000000100c4 : mv a1,a0 0x00000000000100c8 : lui a0,0x21 0x00000000000100cc : addi a0,a0,-192 # 0x20f40 0x00000000000100d0 : jal ra,0x10418 0x00000000000100d4 : ld ra,8(sp) 0x00000000000100d8 : li a0,0 0x00000000000100dc : addi sp,sp,16 0x00000000000100e0 : ret End of assembler dump. (gdb) disass sum Dump of assembler code for function sum: 0x00000000000101b8 : addw a0,a0,a1 0x00000000000101bc : ret End of assembler dump.

View on Compiler Explorer

In just this small example, we see multiple…
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