SiFive's brand-new P550 is one of the world's fastest RISC-V CPUs

arstechnica.com
5 min read
fairly difficult
Today's RISC-V microcontrollers may lead to future RISC-V phones and laptops.
Today, RISC-V CPU design company SiFive launched a new processor family with two core designs: P270 (a Linux-capable CPU with full support for RISC-V's vector extension 1.0 release candidate) and P550 (the highest-performing RISC-V CPU to date).

A quick RISC-V overview

For those not immediately familiar with RISC-V, it is a relatively new CPU architecture which takes advantage of Reduced Instruction Set Computer (RISC) principles. RISC-V is an open standard specifically designed to be forward-looking and evade as much legacy cruft as possible. One example of this design is RISC-V's dynamic width vector instruction set, which allows developers to execute vector instructions on data of arbitrary size with maximum efficiency.

In traditional processor designs, a vector instruction has a fixed width tied to the hardware register size of the processor—for example, SSE and SSE2 allow use of a Pentium III's 128-bit registers, while making full use of an i7-4770's 256-bit registers requires a completely separate instruction set (AVX2) for the same mathematical operations. Moving up to an i7-1065G7's 512-bit registers requires yet another instruction set, AVX-512—again, for the same underlying mathematical operations.

In sharp contrast, RISC-V vector math allows a single set of CPU instructions to perform the same set of mathematical operations as efficiently as possible, using whatever size registers the current CPU design has available. This means a developer can simply write a single routine that will process vector operations as efficiently as possible on a phone with 64-bit registers or on a supercomputer with 1,024-bit registers.

In addition to forward-looking features built into the RISC-V spec, the architecture is designed to provide flexibility that its designers did not or could not think of ahead of time. Generic RISC-V designs feature reserved opcodes, which designers of specific RISC-V CPUs may then take over to provide additional, arbitrary…
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