SimEng — SimEng documentation

uob-hpc.github.io
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Article URL: https://uob-hpc.github.io/SimEng/ Comments URL: https://news.ycombinator.com/item?id=28767344 Points: 1 # Comments: 0
The Simulation Engine - SimEng¶

SimEng is a framework for building modern, cycle-accurate processor simulators. Its goals are to be:

Fast, typically 4-5X faster than gem5

Easy to use and modify to model desired microarchitecture configurations. New cores can be configured in just a few hours

Scalable, from simple scalar microarchitectures up to the most sophisticated, superscalar, out-of-order designs

Capable of supporting a wide range of instruction set architectures (ISAs), starting with Armv8 but eventually including RISC-V, x86, POWER, etc.

Accurate, aiming for simulated cycle times being within 5-10% of real hardware

Open source, with a permissive license to enable collaboration across academia and industry

SimEng places an emphasis on performance and ease of use, whilst maintaining a clean, modern, simple and well-documented code base. For example, the current out-of-order (OoO) model is implemented in around 10,000 lines of simple C++, with another 9,000 lines or so implementing the specifics of the Armv8 ISA, and around 13,000 lines of code in the accompanying test suite. SimEng should be simple to read and understand, making it ideal to modify to your requirements and include it in your projects.

Features¶ Currently, SimEng targets the Armv8+SVE ISA with the ability to model up to out-of-order, superscalar, single-core processors, and to emulate a…
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