The first HPC chip built on TSMC's 2nm process node will arrive in 2026
AMD shows off its first 2nm-class Venice CPU die built using TSMC's N2 node Venice, built on Zen 6, targets high-performance computing workloads AMD and TSMC hope to deepen their collaboration for future innovations AMD has announced it has successfully produced the first 2nm-class silicon for its next-generation EPYC processor, codenamed "Venice" which is expected to launch in 2026 as part of AMD's 6th Generation EPYC lineup. The core complex die (CCD) is the first high-performance computing product to be taped out and brought up using TSMC's advanced N2 process technology. The Venice CPU, built on the Zen 6 architecture, brings AMD one step closer to delivering on its data center roadmap and will target HPC workloads when it launches. With the move to the 2nm node, AMD expects to offer better power efficiency, performance, and…